The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge. In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits. CMOS logic circuits utilizing subthreshold transistors can operate with very low power consumption. In this type of circuits, the power dissipation is mainly due to the dynamic (switching) power consumption and is quadratically dependent to the supply voltage. Hence, reducing the supply voltage will result in reduction of power dissipation as well as the output logic swing. Supply voltage reduction, on the other hand, increases the delay in each gate which means the power dissipation, logic swing, and speed of operation are tightly related to each other. Meanwhile, the exponential relationship between power dissipation and supply voltage in sub-threshold regime makes the accurate control of power consumption difficult. To implement very low power digital systems, it is necessary to minimize the energy dissipation at the system level in addition to the gate level to achieve the desired performance.
[read on]
|
