Project Description

This project is addressing the power dissipation as the greatest challenge for today\'s nanoelectronics, from a novel device and circuit hybrid design perspective. Tunnel FETs are steep slope switches that address critical power issues (especially the subthreshold power) in today.s and future nanoelectronics and are considered in research and industry as the candidate with the highest potential for low power circuits and systems. However, to achieve its full potential it is required to establish the modeling and simulation environment to understand the physics, optimize the device performance and be able to fully exploit the tunnel FET performance on the circuit and system level.  

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Simulation Study of Nanowire Tunnel FETs (Invited)
A. Schenk, Reto Rhyner, Mathieu Luisier, and Cedric Bessire
Digest of 70th Device Research Conference (DRC), June 18-20, pp. 201-202, 2012

A High Polynomial-Order Wavelet Method for Semiconductor Transport Equations
V. Peikert and A. Schenk
Proc. 15th International Workshop on Computational Electronics (IWCE-15), University of Wisconsin, Madison, May 22-25, pp. 35 - 36, 2012

Silicon Nanowire Esaki Diodes
Heinz Schmid, Cedric Bessire, Mikael T. Björk, A. Schenk, and Heike Riel
Nano Lett. 12 (2), 699 - 703, 2012. doi:10.1021/nl2035964

A Wavelet Method to Solve High-dimensional Transport Equations in Semiconductor Devices
V. Peikert and A. Schenk
Proc. 11th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Osaka, Japan, Sep. 8 - 10, 2011, pp. 299 - 302


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